This paper presents an approach to perform automatic stepping and probing on arrays of D2D stacks pick-n-placed (PnP) on a carrier substrate. An algorithm will be described for the Cascade Microtech CM300 probe station to automatically correct small PnP misalignments. Experimental results will be presented on three types of carriers: (1) dicing tape on tape frames for Ø 100 mm wafers, (2) sheets of single-sided thermal-release tape, and (3) Ø 300 mm carrier wafers with double-sided thermal-release tape.
Engineers deal with architectures and multi-functional ICs that continuously decrease physical dimensions, while operation frequencies and levels of integration complexity increase. Learn how they achieve high levels of accuracy and confidence in measurement results.
Shrinking semiconductor geometries with reduced reliability margins demand a highly accurate method for modeling EM effects to produce proper IC design rules. CVEM offers a precise solution to avoid these pitfalls and enable IC manufacturers to continue offering aggressive performance specifications without sacrificing quality.
Pushing device operation frequencies towards the sub-THz range causes serious challenges for conventional device characterization techniques. This application note presents a comparison of SOLT, NIST multiline TRL, and LRRM probe-tip calibration methods for accuracy of measured and extracted figure of merits (FoM) of advanced BiCMOS HBT. A good understanding of possible sources of errors and potential room for improvement at each step are key to increasing the accuracy of device characterization. This paper will show why eLRRM is recommended as an accurate, consistent and easy to implement probe tip calibration method for characterization of advanced high-performance active devices.
Experiments show the technical feasibility of the direct probing approach, with probe tips making proper electrical contact to the micro-bumps, causing only limited probe marks and no measureable impact on stack interconnect yield. Cost modeling indicates economic feasibility for single-site testing, with the next step to prepare the technology for volume production.
A new method is proposed for calibrating multichannel probes placed in multiple quadrants for wafer or chip level measurement. It uses an additional ground-signal-ground probe to enable thru measurements in a conventional calibration procedure, avoiding the need for custom calibration kits. The inherent delay inconsistencies in the proposed method are shown to be small enough to have minimal effects on the measurement uncertainties, in most practical cases.