Leading researchers are raising doubts that CIEM will be sufficient and appropriate for evaluating electromigration on tomorrow’s highly scaled copper lines and vias. Learn more about the emerging challenges to CIEM revealed by interconnect technology evolution.
Pushing device operation frequencies towards the sub-THz range causes serious challenges for conventional device characterization techniques. This application note presents a comparison of SOLT, NIST multiline TRL, and LRRM probe-tip calibration methods for accuracy of measured and extracted figure of merits (FoM) of advanced BiCMOS HBT. A good understanding of possible sources of errors and potential room for improvement at each step are key to increasing the accuracy of device characterization. This paper will show why eLRRM is recommended as an accurate, consistent and easy to implement probe tip calibration method for characterization of advanced high-performance active devices.
Direct micro-bump probing is proving to be a more cost-effective and technologically complete method than dedicated prebond probe pads. However, it requires advanced probe cards and probe stations. Recent work on test wafers has resulted in successfully probing single-channel wide-I/O micro-bumps at 25 μm diameter. Work continues to further prove out this methodology on actual Wide-I/O DRAM.
A new method is proposed for calibrating multichannel probes placed in multiple quadrants for wafer or chip level measurement. It uses an additional ground-signal-ground probe to enable thru measurements in a conventional calibration procedure, avoiding the need for custom calibration kits. The inherent delay inconsistencies in the proposed method are shown to be small enough to have minimal effects on the measurement uncertainties, in most practical cases.